PIC16C711-20/SO【PDF 15/177 页】IC MCU OTP 1KX14 A/D 18SOIC

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Sheet目录3861

11页 12页 13页 14页 [15页]16页 17页 18页 19页

111

7593L–AVR–09/12

AT90USB64/128

Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 14-7. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) modes (see “Modes of operation” on page 103).

Notes:

1. MAX

= 0xFF

2. BOTTOM = 0x00

14.8.2

TCCR0B – Timer/Counter Control Register B

Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is

changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a

strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the

forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0A as TOP.

The FOC0A bit is always read as zero.

Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is

changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a

Table 14-7.

Waveform Generation Mode bit description.

Mode

WGM2

WGM1

WGM0

Timer/Counter mode of

operation

TOP

Update of

OCRx at

TOV flag

set on

(1)(2)

Normal

0xFF

Immediate

MAX

PWM, phase correct

0xFF

TOP

BOTTOM

CTC

OCRA

Immediate

MAX

Fast PWM

0xFF

TOP

MAX

Reserved

–

PWM, phase correct

OCRA

TOP

BOTTOM

Reserved

–

Fast PWM

OCRA

TOP

Bit

543

FOC0A

FOC0B

–

WGM02

CS02

CS01

CS00

TCCR0B

Read/write

R/W

Initial value

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